A sequence detector is designed to detect precisely 3 digital inputs, with overlapping sequences detectable. For the sequence (1,0,1) and input data (1,1,0,1,0,0,1,1,0,1,0,1,1,0), what is the output of this detector?

For the synchronous sequential circuit shown below, the output Z is zero for the initial conditions

The minimum number of clock cycles after which the output Z would again become zero is ___________.

In the following sequential circuit, the initial state (before the first clock pulse) of the circuit is . The state , immediately after the 333rd clock pulse is

The state transition diagram for the logic circuit shown is

The digital circuit shown in figure works as a