Loading...

Loading, please wait...

Back to Topics

Digital Electronics
Data Converters

Practice questions from Data Converters.

22
Total
0
Attempted
0%
0
Correct
0%
0
Incorrect
0%
Q#1 Data Converters GATE EE 2023 (Set 1) MCQ +2 marks -0.66 marks

An 8-bit ADC converts analog voltage in the range of 0 to  to the corresponding digital code as per the conversion characteristics shown in figure. For , which of the following digital output, given in hex, is true?

64 H

65 H

66 H

67 H

Explanation Locked!

Unlock this branch to view the explanation, track, bookmark and more.

Sign in to Unlock
Q#2 Data Converters GATE EE 2016 (Set 1) MCQ +1 mark -0.33 marks

A temperature in the range of  is to be measured with a resolution of . The minimum number of ADC bits required to get a matching dynamic range of the temperature sensor is

8

10

12

14

Explanation Locked!

Unlock this branch to view the explanation, track, bookmark and more.

Sign in to Unlock
Q#3 Data Converters GATE EE 2016 (Set 1) MCQ +2 marks -0.66 marks

A 2-bit flash Analog to digital converter (ADC) is given below. The input is  Volts. The expression for the LSB of the output  as a Boolean function of  and  is

 

Explanation Locked!

Unlock this branch to view the explanation, track, bookmark and more.

Sign in to Unlock
Q#4 Data Converters GATE EE 2015 (Set 1) MCQ +2 marks -0.66 marks

An 8-bit, unipolar successive approximation register type ADC is used to convert 3.5V to digital equivalent output. The reference voltage is +5V. The output of the ADC, at the end of 3rd clock pulse after the start of conversion, is

1010 0000

1000 0000

0000 0001

0000 0011

Explanation Locked!

Unlock this branch to view the explanation, track, bookmark and more.

Sign in to Unlock
Q#5 Data Converters GATE EE 2008 (Set 1) MCQ +1 mark -0.33 marks

Two 8-bit ADCs, one of single slope integrating type and other of successive approximation type, take and times to convert 5V analog input signal to equivalent digital output. If the input analog signal is reduced to 2.5V, the approximate lime taken by the two ADCs will respectively be

Explanation Locked!

Unlock this branch to view the explanation, track, bookmark and more.

Sign in to Unlock
Q#6 Data Converters GATE EE 2006 (Set 1) MCQ +2 marks -0.66 marks

A student has made a 3-bit binary down counter and connected to the R- 2R ladder type DAC [Gain = (-1 kΩ/2R)] as shown in figure to generate a staircase waveform.  The output achieved is different as shown in figure.  What could be the possible cause of this error?

 

The resistance values are incorrect

The counter is not working properly

The connection from the counter to DAC is not proper

The R and 2R resistances are interchanged

Explanation Locked!

Unlock this branch to view the explanation, track, bookmark and more.

Sign in to Unlock
Q#7 Data Converters GATE EE 2006 (Set 1) MCQ +2 marks -0.66 marks

It is required to design an anti-aliasing filter for an 8 bit ADC.  The filter is a first order RC filter with R = 1Ω and C = 1F.  The ADC is designed to span a sinusoidal signal with peak to peak amplitude equal to the full range of the ADC.

The transfer function of the filter and its roll off respectively are

dB/decade

dB/decade

dB/decade

dB/decade

Explanation Locked!

Unlock this branch to view the explanation, track, bookmark and more.

Sign in to Unlock
Q#8 Data Converters GATE EE 2006 (Set 1) MCQ +2 marks -0.66 marks

It is required to design an anti-aliasing filter for an 8 bit ADC.  The filter is a first order RC filter with R = 1W and C = 1F.  The ADC is designed to span a sinusoidal signal with peak to peak amplitude equal to the full range of the ADC.

What is the SNR (in dB) of the ADC? Also find the frequency (in decades) at the filter output at which the filter attenuation just exceeds the SNR of the ADC.

50 dB, 2 decades

50 dB, 2.5 decades

60 dB, 2 decades

60 dB, 2.5 decades

Explanation Locked!

Unlock this branch to view the explanation, track, bookmark and more.

Sign in to Unlock
Q#9 Data Converters GATE EE 2005 (Set 1) MCQ +1 mark -0.33 marks

A digital-to-analog converter with a full-scale output voltage of 3.5V has a resolution close to 14 mV. Its bit size is:

4

8

16

32

Explanation Locked!

Unlock this branch to view the explanation, track, bookmark and more.

Sign in to Unlock
Q#10 Data Converters GATE EE 2004 (Set 1) MCQ +1 mark -0.33 marks

The voltage comparator shown in figure can be used in as

 

A 1-bit quantizer

A 2-bit quantizer

A 4-bit quantizer

A 8-bit quantizer

Explanation Locked!

Unlock this branch to view the explanation, track, bookmark and more.

Sign in to Unlock
Q#11 Data Converters GATE EE 2003 (Set 1) MCQ +2 marks -0.66 marks

The simplified block diagram of a 10-bit A/D converter of dual slope integrator type is shown in figure. The 10-bit counter at the output is clocked by a 1MHz clock. Assuming negligible timing overhead for the control logic, the maximum frequency of the analog signal that can be converted using this A/D converter is approximately

 

2 kHz

1 kHz

500 Hz

250 Hz

Explanation Locked!

Unlock this branch to view the explanation, track, bookmark and more.

Sign in to Unlock
Q#12 Data Converters GATE EE 2001 (Set 1) MCQ +1 mark -0.33 marks

Among the following four, the slowest ADC (analog-to-digital converter) is

Parallel comparator (i.e., flash) type

Successive approximation type

Integrating type

Counting type

Explanation Locked!

Unlock this branch to view the explanation, track, bookmark and more.

Sign in to Unlock
Q#13 Data Converters GATE EE 2001 (Set 1) MCQ +2 marks -0.66 marks

A sample-and-hold (S/H) circuit, having a holding capacitor of 0.1nF, is used at the input of an ADC (analog-to-digital converter).  The conversion time of the ADC is 1µsec, and during this time, the capacitor should not lose more than 0.5% of the charge put across it during the sampling time.  The maximum value of the input signal to the S/H circuit is 5V.  The leakage current of the S/H circuit should be less than

2.5 mA

0.25 mA

25.0 µA

2.5 µA

Explanation Locked!

Unlock this branch to view the explanation, track, bookmark and more.

Sign in to Unlock
Q#14 Data Converters GATE EE 2000 (Set 1) MCQ +2 marks -0.66 marks

A dual slope analog-to-digit converters uses an N-bit counter. When the input signal  is being integrated, the counter is allowed to count up to a value

Equal to

Equal to

Proportional to

Inversely proportional to

Explanation Locked!

Unlock this branch to view the explanation, track, bookmark and more.

Sign in to Unlock
Q#15 Data Converters GATE EE 1999 (Set 1) MCQ +1 mark -0.33 marks

A single channel digital storage oscilloscope uses a 10 bit,  samples per second Analog-to-Digital converter. For a 100 KHz sine wave input, the number of samples taken per cycle of the input will be

Explanation Locked!

Unlock this branch to view the explanation, track, bookmark and more.

Sign in to Unlock
Q#16 Data Converters GATE EE 1999 (Set 1) MCQ +2 marks -0.66 marks

For a dual ADC type  digit DVM, the reference voltage is 100mV and the first integration time is set to 300ms. For some input voltage, the “de-integration” period is 370.2ms. The DVM will indicate

123.4

199.9

100.0

1.141

Explanation Locked!

Unlock this branch to view the explanation, track, bookmark and more.

Sign in to Unlock
Q#17 Data Converters GATE EE 1995 (Set 1) MCQ +1 mark -0.33 marks

A  digit, 2 V full scale slope ADC has its integration time set to 300ms. If the input to the ADC is (1+1sin314t)V, then the ADC output will be

1.000

1.999

1.414

1.500

Explanation Locked!

Unlock this branch to view the explanation, track, bookmark and more.

Sign in to Unlock
Q#18 Data Converters GATE EE 1994 (Set 1) MCQ +1 mark -0.33 marks

The number of comparisons carried out in a 4-bit flash-type A/D converter is_________?

16

15

4

3

Explanation Locked!

Unlock this branch to view the explanation, track, bookmark and more.

Sign in to Unlock
Q#19 Data Converters GATE EE 1993 (Set 1) MCQ +1 mark -0.33 marks

A 10 bit A/D converter is used to digitize an analog signal in the 0 to 5V range. The maximum peak to peak ripple voltage that can be allowed in the D.C. supply voltage is

Nearly 100 mV

Nearly 50 mV

Nearly 25 mV

Nearly 5.0 mV

Explanation Locked!

Unlock this branch to view the explanation, track, bookmark and more.

Sign in to Unlock
Q#20 Data Converters GATE EE 1992 (Set 1) MCQ +1 mark -0.33 marks

The number of comparators needed in a parallel conversion type 8-bit A to D converter is

8

16

255

256

Explanation Locked!

Unlock this branch to view the explanation, track, bookmark and more.

Sign in to Unlock
Q#21 Data Converters GATE EE 1992 (Set 1) NAT +2 marks -0 marks

In a dual slope integrating type digital voltmeter the first integration is carried out for 10 periods of the supply frequency of 50 Hz. If the reference voltage used is 2 V, the total conversion time for an input 1V is ___________ sec

Explanation Locked!

Unlock this branch to view the explanation, track, bookmark and more.

Sign in to Unlock
Q#22 Data Converters GATE EE 1991 (Set 1) NAT +2 marks -0 marks

The resolution of an 8-bit A/D converter is ________________%

Explanation Locked!

Unlock this branch to view the explanation, track, bookmark and more.

Sign in to Unlock