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Network Analysis
Sinusoidal Steady State Analysis
Miscellaneous

Questions mapped to Miscellaneous under Sinusoidal Steady State Analysis.

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Q#1 Sinusoidal Steady State Analysis GATE EE 2023 (Set 1) NAT +2 marks -0 marks

The circuit shown in the figure is initially in the steady state with the switch  in open condition and  in closed condition. The switch  is closed and  is opened simultaneously at the instant , where . The minimum value of  in milliseconds, such that there is no transient in the voltage across the  capacitor, is (Round off to 2 decimal places).

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Q#2 Sinusoidal Steady State Analysis GATE EE 2009 (Set 1) MCQ +2 marks -0.66 marks

The equivalent capacitance of the input loop of the circuit shown is

Q24.jpg

2 µF

100 µF

200 µF

4 µF

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Q#3 Sinusoidal Steady State Analysis GATE EE 1991 (Set 1) MCQ +2 marks -0.66 marks

A one port active network has an input admittance Y, the magnitude of which is shown in figure as a function of frequency. The circuit is resistive or capacitive in different frequency ranges.

Complete the following table:

Frequency Range

Type of Impedance

Value (Ω/H/F)

10000 rad/sec < ω

A

P

10 rad/sec < ω < 1000 rad/sec

B

Q

D:\Vol-2\SSSA-03.jpg

A= Capacitive, P=C=10μF and B=Inductive  Q=L=0.01H

A= Capacitive, P=C=100μF and B=Inductive  Q=L=0.1H

A=Inductive  P=L=0.01H and B=Capacitive  Q=C=100μF

A= Capacitive, P=C=100μF and B=Inductive  Q=L=0.01H

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