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Q#1
Data Converters
GATE EE 2001
MCQ
+2 marks
-0.66 marks
A sample-and-hold (S/H) circuit, having a holding capacitor of 0.1nF, is used at the input of an ADC (analog-to-digital converter). The conversion time of the ADC is 1µsec, and during this time, the capacitor should not lose more than 0.5% of the charge put across it during the sampling time. The maximum value of the input signal to the S/H circuit is 5V. The leakage current of the S/H circuit should be less than
2.5 mA
0.25 mA
25.0 µA
2.5 µA
Explanation:
Change in voltage during sampling time = 0.5% of 5V
Leakage current through the capacitor = 
Where 
is the sampling time
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