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Analog Electronics
MOSFET
DC Analysis and Biasing Circuits of MOSFET

Questions mapped to DC Analysis and Biasing Circuits of MOSFET under MOSFET.

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Q#1 MOSFET GATE EE 2020 (Set 1) NAT +1 mark -0 marks

The cross-section of a metal-oxide-semiconductor structure is shown schematically. Starting from an uncharged condition, a bias of +3 V is applied to the gate contact with respect to the body contact. The charge inside the silicon dioxide layer is then measured to be +Q. The total charge contained within the dashed box shown, upon

application of bias, expressed as a multiple of Q (absolute value in Coulombs, rounded off to the nearest integer) is ___________.

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Q#2 MOSFET GATE EE 2019 (Set 1) MCQ +1 mark -0.33 marks

Given  is the gate-source voltage,  is the drain source voltage, and  is the threshold voltage of an enhancement type NMOS transistor, the conditions for transistor to be biased in saturation are

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Q#3 MOSFET GATE EE 2019 (Set 1) MCQ +2 marks -0.66 marks

The enhancement type MOSFET in the circuit below operates according to the square law. , the threshold voltage  is 500 mV. Ignore channel length modulation. The output voltage  is

D:\Tiff\CH-6\(Q53 )EE 2019 (Naveen).png

500 mV

600 mV

2 V

100 mV

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Q#4 MOSFET GATE EE 2005 (Set 1) MCQ +1 mark -0.33 marks

Assume that the N-channel MOSFET shown in Figure is ideal, and that its threshold voltage is +1.0V. The voltage  between nodes a and b is:

5V

2V

1V

0V

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Q#5 MOSFET GATE EE 2005 (Set 1) MCQ +2 marks -0.66 marks

The charge distribution in a metal-dielectric-semiconductor specimen is shown in Figure.  The negative charge density decreases linearly in the semiconductor as shown. The electric field distribution is as shown in        

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Q#6 MOSFET GATE EE 2004 (Set 1) MCQ +2 marks -0.66 marks

The value of R for which the PMOS transistor in figure will be biased in linear region is

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Q#7 MOSFET GATE EE 2003 (Set 1) MCQ +1 mark -0.33 marks

The variation of drain current with gate-to-source voltage ( characteristic) of a MOSFET is shown in Figure. The MOSFET is

An n-channel depletion mode device

An n-channel enhancement mode device

A p-channel depletion mode device

A p-channel enhancement mode device

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Q#8 MOSFET GATE EE 2003 (Set 1) MCQ +2 marks -0.66 marks

For the n-channel enhancement MOSFET shown in Figure, the threshold voltage . The drain current  of the MOSFET is 4 mA when the drain resistance  is . If the value of  is increased to , drain current  will become

2.8 mA

2.0 mA

1.4 mA

1.0 mA

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Q#9 MOSFET GATE EE 2001 (Set 1) MCQ +2 marks -0.66 marks

An n-channel JFET, having a pinch off voltage  of −5V, shows a trans-conductance  of 1mA/V when the applied gate-to-source voltage  is -3V.  Its maximum trans-conductance (in mA/V) is

1.5

2.0

2.5

3.0

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Q#10 MOSFET GATE EE 1999 (Set 1) MCQ +1 mark -0.33 marks

An enhancement type n-channel MOSFET is represented by the symbol

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