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Sinusoidal Steady State Analysis
Phasor Analysis

Questions mapped to Phasor Analysis under Sinusoidal Steady State Analysis.

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Q#1 Sinusoidal Steady State Analysis GATE EE 2023 (Set 1) NAT +2 marks -0 marks

For the circuit shown, if , the instantaneous value of the Thevenin's equivalent voltage (in Volts) across the terminals  at time  is __________ (Round off to 2 decimal places).

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Q#2 Sinusoidal Steady State Analysis GATE EE 2021 (Set 1) NAT +1 mark -0 marks

In the given circuit, the value of capacitor C that makes current I = 0 is _________ μF.

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Q#3 Sinusoidal Steady State Analysis GATE EE 2020 (Set 1) NAT +1 mark -0 marks

Current through ammeters  and  in fig. are 1  10° and 1  70° respectively. The reading of the ammeter A1 (rounded off to 3 decimal places) is _________ A.

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Q#4 Sinusoidal Steady State Analysis GATE EE 2018 (Set 1) NAT +2 marks -0 marks

The voltage v(t) across the terminals a and b as shown in the figure, is a sinusoidal voltage having a frequency . When the inductor current i(t) is in phase with the voltage v(t), the magnitude of the impedance Z (in ) seen between the terminals a and is _______ (up to 2 decimal places).

Untitled-11.png

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Q#5 Sinusoidal Steady State Analysis GATE EE 2018 (Set 1) MCQ +2 marks -0.66 marks

The equivalent impedance for the infinite ladder circuit shown in the figure is

Untitled-30.png

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Q#6 Sinusoidal Steady State Analysis GATE EE 2016 (Set 1) NAT +2 marks -0 marks

In the circuit shown below, the supply voltage is  volts. The peak value of the steady state current through the  resistor, in amperes, is _________________.  

C:\Users\Ankit\Dropbox\GATE papers\EE papers\Typed\Gate-EE-2016\EE_GATE_2016_SET_1\EE_GATE_2016_SET_1 image\22.jpg

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Q#7 Sinusoidal Steady State Analysis GATE EE 2016 (Set 2) MSQ +1 mark -0.33 marks

A resistance and a coil connected in series and supplied from a phase, 100V, 50Hz ac source as shown in the figure below. The rms values of possible voltages across the resistance  and coil  respectively, in volts are

4.jpg`

65, 35

50, 50

60, 90

60, 80

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Q#8 Sinusoidal Steady State Analysis GATE EE 2015 (Set 1) NAT +2 marks -0 marks

The circuit shown in the figure has two sources connected in series. The instantaneous voltage of the AC source (in Volt) is given by . If the circuit is in steady state, then the RMS value of the current (in Ampere) flowing in the circuit is

27.jpg

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Q#9 Sinusoidal Steady State Analysis GATE EE 2015 (Set 2) MCQ +2 marks -0.66 marks

In the given network. , ,  

The phasor current i (in Ampere) is

33.jpg

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Q#10 Sinusoidal Steady State Analysis GATE EE 2014 (Set 2) MCQ +2 marks -0.66 marks

The voltage across the capacitor, as shown in the figure, is expressed as +

10.jpg

The values of and  respectively, are

2.0 and 1.98

2.0 and 4.20

2.5 and 3.50

5.0 and 6.40

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Q#11 Sinusoidal Steady State Analysis GATE EE 2012 (Set 1) MCQ +1 mark -0.33 marks

In the circuit shown below, the current through the inductor is         

0 A

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Q#12 Sinusoidal Steady State Analysis GATE EE 2011 (Set 1) MCQ +1 mark -0.33 marks

The RMS value of the current i(t) in the circuit shown below is

C:\Users\Ankit\Dropbox\GATE papers\EE papers\Typed\Gate-EE-2011\GATE-Electrical-Engineering-2011 images\1.jpg

1A

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Q#13 Sinusoidal Steady State Analysis GATE EE 2011 (Set 1) MCQ +1 mark -0.33 marks

The voltage applied to a circuit is   volts and the circuit draws a current of  amperes. Taking the voltage as the reference phasor, the phasor representation of the current in amperes is

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Q#14 Sinusoidal Steady State Analysis GATE EE 2011 (Set 1) MCQ +2 marks -0.66 marks

An RLC circuit with relevant data is given below.

The current in the figure above is

–j 2A

+j2 A

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Q#15 Sinusoidal Steady State Analysis GATE EE 2007 (Set 1) MCQ +2 marks -0.66 marks

In the figure given below all phasors are with reference to the potential at point "O". The locus of voltage phasor   as R is varied from zero to infinity is shown by

Q63-1.jpg

Q63-2.jpg

Q63-3.jpg

Q63-4.jpg

Q63-5.jpg

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Q#16 Sinusoidal Steady State Analysis GATE EE 2005 (Set 1) MCQ +1 mark -0.33 marks

The RMS value of the voltage is:

5V

7V

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Q#17 Sinusoidal Steady State Analysis GATE EE 2005 (Set 1) MCQ +2 marks -0.66 marks

The RL circuit of Figure is fed from a constant magnitude, variable frequency sinusoidal voltage source . At 100 Hz, the R and L elements each have a voltage drop . If the frequency of the source is changed to 50 Hz, the new voltage drop across R is:

Q31.jpg

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Q#18 Sinusoidal Steady State Analysis GATE EE 2004 (Set 1) MCQ +2 marks -0.66 marks

In figure, the admittance values of the elements in Siemens are

respectively.

The value of I as a phasor when the voltage E across the elements isis

1.5 + j0.5

5 – j18

0.5 + j1.8

5 – j12

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Q#19 Sinusoidal Steady State Analysis GATE EE 2003 (Set 1) MCQ +1 mark -0.33 marks

A segment of a circuit is shown in Figure.  , . The voltage  is given by

C:\Users\Ankit\Dropbox\GATE papers\EE papers\Typed\Gate-EE-2003\Figures\Q2.jpg

3 – 8 cos2t

32 sin2t

16 sin2t

16 cos2t

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Q#20 Sinusoidal Steady State Analysis GATE EE 2000 (Set 1) MCQ +2 marks -0.66 marks

The impedance seen by the source in the circuit in figure, is given by

D:\Vol-2\SSSA-19.jpg

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Q#21 Sinusoidal Steady State Analysis GATE EE 1999 (Set 1) MCQ +1 mark -0.33 marks

The current in the circuit shown in figure is:

C:\Users\Ankit\Dropbox\GATE papers\EE papers\Typed\Gate-EE-1999\images\Q1_1.12.jpg

5A

10A

15A

25A

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Q#22 Sinusoidal Steady State Analysis GATE EE 1999 (Set 1) MCQ +2 marks -0.66 marks

A fixed capacitor of reactance –j0.02 kΩ is connected in parallel across a series combination of a fixed inductor of reactance j0.01 kΩ and a variable resistance R. As R is varied from zero to infinity, the locus diagram of the admittance of this L-C-R circuit will be

A semi-circle of diameter j 100 and center at zero

A semi-circle of diameter j 50 and center at zero

A straight line inclined at an angle

A straight line parallel to the x-axis

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Q#23 Sinusoidal Steady State Analysis GATE EE 1998 (Set 1) MCQ +1 mark -0.33 marks

A sinusoidal source of voltage V and frequency f is connected to a series circuit of variable resistance, R and a fixed reactance, X. the locus of the tip of the current-phasor I, as R is varied from 0 to ∞ is:

A semicircle with a diameter of

A straight line with a slop of

An ellipse with  as major axis

A circle of radius   and origin at  

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Q#24 Sinusoidal Steady State Analysis GATE EE 1994 (Set 1) NAT +1 mark -0 marks

In the given circuit, the voltage , has a phase angle of _____________ with respect to .

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