A MOD 2 and a MOD 5 up-counter when cascaded together results in a MOD ______ counter. (in integer)

The maximum clock frequency in MHz of a 4-stage ripple counter, utilizing flipflops, with each flip-flop having a propagation delay of 20 ns, is ___________. (round off to one decimal place)

A 16-bit synchronous binary up-counter is clocked with a frequency fCLK. The two most significant bits are OR-ed together to form an output Y. Measurements show' that Y is periodic, and the duration for which Y remains high in each period is 24 ms. The clock frequency fCLK is _________ MHz. (Round off to 2 decimal places.)

A counter is constructed with three D flip-flops. The input-output pairs are named (D0, Q0), (D1, Q1), and (D2, Q2), where the subscript 0 denotes the least significant bit. The output sequence is desired to be the Gray-code sequence 000, 001, 011, 010, 110, 111, 101, and 100, repeating periodically. Note that the bits are listed in the Q2 Q1 Q0 format. The combinational logic expression for D1 is

The figure shows a digital circuit constructed using negative edge triggered J – K flip flops. Assume a starting state of . This state  will repeat after __________ number cycles of the clock CLK.

A cascade of three identical modulo – 5 counters has an overall module of

Which of the following is an invalid state in an 8-4-2-1 Binary coded decimal counter

A 3-bit gray counter is used to control the output of the multiplexer as shown in the figure. The initial state of the counter is . The output is pulled high. The output of the circuit follows the sequence

The clock frequency applied to the digital circuit shown in the figure below is 1 kHz. If the initial state of the output Q of the flip-flop is 0, then the frequency of the output waveform Q in kHz is

two-bit counter circuit is shown below.

If the state  of the counter at the clock time  is “10” then the state  of the counter at  (after three clock cycles) will be

The ripple counter shown in figure is made up negative edge triggered J-K flips flops. The signal levels at J and K inputs of all the flip-flops are maintained at logic 1. Assume that all outputs are cleared just prior to applying the clock signal.

(a)        Create a table of Q0, Q1, Q2 and A in the format given below for 10 successive input cycles of the clock CLK1.

(b)        Determine the module number of the counter.

(c)        Modify the circuit of given figure to create a module-6 counter using the same components used in the figure.

For the ring counter shown in figure, find the steady state sequence if the initial state of the counters is 1110 (i.e., Q3, Q2, Q1, Q0 = 1110).  Determine the MOD number of the counter.

The counter shown in the figure, is initially in state . With reference to the CLK input, draw waveforms for  and P for the next three CLK cycles.

(a)        Construct the truth table for the circuit given.   are outputs and the clock pulses are the inputs. Unused J, K inputs are assumed to be at logic 1. All flip-flops are rest at power ON.

(b)        Sketch the output waveforms at  

(c)         What function does this circuit perform?

The three stage Johnson ring counter shown in figure is clock at a constant frequency of  from the starting stage of . The frequency of outputs  will be