The ripple counter shown in figure is made up negative edge triggered J-K flips flops. The signal levels at J and K inputs of all the flip-flops are maintained at logic 1. Assume that all outputs are cleared just prior to applying the clock signal.

(a)        Create a table of Q0, Q1, Q2 and A in the format given below for 10 successive input cycles of the clock CLK1.

(b)        Determine the module number of the counter.

(c)        Modify the circuit of given figure to create a module-6 counter using the same components used in the figure.