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The ripple counter shown in figure is made up negative edge triggered J-K flips flops. The signal levels at J and K inputs of all the flip-flops are maintained at logic 1. Assume that all outputs are cleared just prior to applying the clock signal.
(a) Create a table of Q0, Q1, Q2 and A in the format given below for 10 successive input cycles of the clock CLK1.
(b) Determine the module number of the counter.
(c) Modify the circuit of given figure to create a module-6 counter using the same components used in the figure.
(a)
(b) Mod-8 counter
(c) The NAND gate input should be changed to 
instead of 
.
i.e. A
(a)
(b) Mod-6 counter
(c) The NAND gate input should be changed to instead of .
i.e. A
(a)
(b) Mod-5 counter
(c) The NAND gate input should be changed to instead of .
i.e. A
None
Given all the flip flops are negative edge triggered and in toggle mode. [J=1, K=1 Q (n+1)=
Q1 Toggles whenever Q0 changes from 1 to 0 and similarly Q2 Toggles whenever Q1 changes
from 1 to 0.
Output of the NAND gate A 
When both Q2 and Q0 are logic 1 then only all the three J-K flip flops will be clear i.e. Q=0
Truth Table:
(b) The given circuit is a Mod-5 counter
(c) The NAND gate input should be changed to instead of .
i.e. A
Truth Table:
Now it is a MOD 6 counter