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Digital Electronics
Microprocessor

Practice questions from Microprocessor.

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Q#1 Microprocessor GATE EC 2021 (Set 1) MCQ +2 marks -0.66 marks

The content of the registers are ,  and . The following machine instructions are executed,        

PUSH

PUSH

PUSH

 

 

After execution, the content of registers   are

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Q#2 Microprocessor GATE EC 2020 (Set 1) NAT +1 mark -0 marks

In an 8085 microprocessor, the number of address lines required to access a  byte memory bank is _______.

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Q#3 Microprocessor GATE EC 2017 (Set 1) MCQ +1 mark -0.33 marks

The clock frequency of an 8085 microprocessor is 5 MHz. If the time required to execute an instruction is 1.4 µs, then the number of T-states needed for executing the instruction is

1

6

7

8

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Q#4 Microprocessor GATE EC 2017 (Set 1) MCQ +2 marks -0.66 marks

The following FIVE instructions were executed on an 8085 microprocessor.        

MVI A, 33H

MVI B, 78H

ADD B

CMA

ANI 32 H

The Accumulator value immediately after the execution of the fifth instruction is

00H

10H

11H

32H

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Q#5 Microprocessor GATE EC 2016 (Set 1) MCQ +2 marks -0.66 marks

In an 8085 system, a PUSH operation requires more clock cycles than a POP operation.

Which one of the following options is the correct reason for this?

For POP, the data transceivers remain in the same direction as for instruction fetch (memory to processor), whereas for PUSH their direction has to be reversed.

Memory write operations are slower than memory read operations in an 8085 based system.

The stack pointer needs to be pre-decremented before writing registers in a PUSH, whereas a POP operation uses the address already in the stack pointer.

Order of registers has to be interchanged for a PUSH operation, whereas POP uses their natural order.

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Q#6 Microprocessor GATE EC 2016 (Set 1) MCQ +1 mark -0.33 marks

In an 8085 microprocessor, the contents of the accumulator and the carry flag are A7 (in hex) and 0, respectively. If the instruction RLC is executed, then the contents of the accumulator (in hex) and the carry flag respectively, will be

4E and 0

4E and 1

4F and 0

4F and 1

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Q#7 Microprocessor GATE EC 2015 (Set 1) MCQ +1 mark -0.33 marks

In an 8085 microprocessor, the shift registers which store the result of an addition and the overflow bit are, respectively

B and F

A and F

 H and F

A and C

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Q#8 Microprocessor GATE EC 2015 (Set 2) MCQ +1 mark -0.33 marks

In an 8085 microprocessor, which one of the following instructions changes the content of the accumulator?        

MOV B,M

PCHL

RNZ

SBI BEH

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Q#9 Microprocessor GATE EC 2014 (Set 2) MCQ +2 marks -0.66 marks

For the 8085 microprocessor, the interfacing circuit to input 8-bit digital data  from an external device is shown in the figure. The instruction for correct data transfer is

MVI A, F8H

IN F8H

OUT F8H

LDA F8F8H

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Q#10 Microprocessor GATE EC 2014 (Set 4) MCQ +2 marks -0.66 marks

An 8085 microprocessor executes “STA 1234H” with starting address location 1FFEH (STA copies the contents of the Accumulator to the 16-bit address location). While the instruction is fetched and executed, the sequence of values written at the address pins  is

1FH, 1FH, 20H, 12H

1FH, FEH, 1FH, FFH, 12H

1FH, 1FH, 12H, 12H

1FH, 1FH, 12H, 20H, 12H

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Q#11 Microprocessor GATE EC 2014 (Set 3) MCQ +1 mark -0.33 marks

Which one of the following 8085 microprocessor programs correctly calculates the product of two 8-bit numbers stored in registers B and C?        

                MVI A, 00H

              JNZ LOOP

              CMP C        

LOOP     DCR B        

              HLT        

                MVI A, 00H

               CMP C

LOOP      DCR B

               JNZ LOOP

               HLT

                 MVI A, 00H

LOOP      ADD C        

               DCR B        

               JNZ LOOP

               HLT

                 MVI A, 00H

               ADD C        

               JNZ LOOP

LOOP      INR B

               HLT

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Q#12 Microprocessor GATE EC 2013 (Set 1) MCQ +1 mark -0.33 marks

For 8085 microprocessor, the following program is executed.

At the end of program, accumulator contains        

17H

20H

23H

05H

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Q#13 Microprocessor GATE EC 2011 (Set 1) MCQ +2 marks -0.66 marks

An 8085 assembly language program is given below. Assume that the carry flag is initially unset. The content of the accumulator after the execution of the program is         

8CH

64H

23H

15H

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Q#14 Microprocessor GATE EC 2010 (Set 1) MCQ +2 marks -0.66 marks

For the 8085 assembly language program given below, the content of the accumulator after the execution of the program is

00H

45H

67H

E7H

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Q#15 Microprocessor GATE EC 2009 (Set 1) MCQ +1 mark -0.33 marks

In microprocessor, the service routine for a certain interrupt starts from a fixed location of memory which cannot be externally set, but the interrupt can be delayed or rejected. Such an interrupt is

non-maskable and non-vectored

maskable and non-vectored

non-maskable and vectored

maskable and vectored

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Q#16 Microprocessor GATE EC 2008 (Set 1) MCQ +2 marks -0.66 marks

An 8085 assembly language program is given below.

After execution of line 7 of the program, the status of the CY and Z flags will be

CY=0, Z=0

CY=0, Z=1

CY=1, Z=0

CY=1, Z=1

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Q#17 Microprocessor GATE EC 2008 (Set 1) MCQ +2 marks -0.66 marks

An 8085 executes the following instructions

2710        LXI         H, 30A0H

2713         DAD        H

2714        PCHL

All addresses and constants are in Hex. Let PC be the contents of the program counter and HL be the contents of the HL register pair just after executing PCHL.

Which of the following statements is correct?        

PC = 2715H

HL = 30A0H

PC = 30A0H

HL = 2715H

PC = 6140H

HL = 6140H

PC = 6140H

HL = 2715H

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Q#18 Microprocessor GATE EC 2007 (Set 1) MCQ +2 marks -0.66 marks

An 8255 chip is interfaced to an 8085 microprocessor system as an I/O mapped I/O as shown in the figure. The address lines  and  of the 8085 are used by the 8255 chip to decode internally its three ports and the Control register. The address lines.  to  as well as signal are used for address decoding. The range of addresses for which the 8255 chip would get selected is

C:\Users\Shreya\AppData\Local\Microsoft\Windows\INetCache\Content.Word\Q46.jpg

F8H – FBH

F8H – FCH 

F8H – FFH

FOH –F7H

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Q#19 Microprocessor GATE EC 2007 (Set 1) MCQ +2 marks -0.66 marks

An 8085 assembly language program is given below.

he contents of the accumulator just after execution of the ADD instruction inline 4 will be

 C3H

EAH

DCH

 69H

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Q#20 Microprocessor GATE EC 2006 (Set 1) MCQ +2 marks -0.66 marks

Following is the segment of a 8085 assembly language program:        

LXI SP, EFFF H

CALL 3000 H

        :

        :

3000 H: LXI H, 3CF4 H

PUSH PSW

SPHL

POP PSW

RET

On completion of RET execution, the contents of SP is

3CFO H        

3CF8 H

3FFD H

EFFF H

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Q#21 Microprocessor GATE EC 2006 (Set 1) MCQ +2 marks -0.66 marks

An I/O peripheral device shown in figure (b) below is to be interfaced to an 8085 microprocessor. To select the I/O device in the I/O address range D4 H – D7 H, its chip-select should be connected to the output of the decoder shown in figure (a) below

Z:\PY\ECE PY\All Updated figure\Digital electronis\P-(367) 38.jpg        

Output 7

Output 5

Output 2

Output 0

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Q#22 Microprocessor GATE EC 2005 (Set 1) MCQ +2 marks -0.66 marks

Consider an 8085-microprocessor system.

The following program starts at location 0100H.

 

The content of accumulator when the program counter reaches 0109H is

20H

02H

00H

FFH

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Q#23 Microprocessor GATE EC 2005 (Set 1) MCQ +2 marks -0.66 marks

Consider an 8085-microprocessor system.
The following program starts at location 0100H.

If in addition following code exists from 0109H onwards.

  ORI 40H

  ADD M

What will be the result in the accumulator after the last instruction is executed?         

40H

20H

60H

42H

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Q#24 Microprocessor GATE EC 2004 (Set 1) MCQ +2 marks -0.66 marks

The 8255 Programmable Peripheral Interface is used as described below.         

I. An A/D converter is interfaced to a microprocessor through an 8255. The conversion is initiated by a signal from the 8255 on port C. A signal on port C causes data to be stored into port A.

II. Two computers exchange data using a pair of 8255s. Port A works as a bi-directional data port supported by appropriate handshaking signals.

The appropriate modes of operation of the 8255 for I and II would be

Mode 0 for I and Mode 1 for II

Mode 1 for I and Mode 2 for II

Mode 2 for I and Mode 0 for II

Mode 2 for I and Mode 1 for II

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Q#25 Microprocessor GATE EC 2004 (Set 1) MCQ +2 marks -0.66 marks

The number of memory cycles required to execute the following 8085 instructions          

I. LDA 3000H

II. LXI D, FOF 1H

Would be

2 for I and 2 for II

4 for I and 3 for II

3 for I and 3 for II

3 for I and 4 for II

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Q#26 Microprocessor GATE EC 2004 (Set 1) MCQ +2 marks -0.66 marks

Consider the sequence of 8085 instructions given below.
LXI H, 9258        
MOV A,M        
CMA        
MOV M,A

Which one of the following is performed by this sequence?  

Contents of location 9258 are moved to the accumulator

Contents of location 9258 are compared with the constants of the accumulator

Contents of location 9528 are complemented and stored in location 9528

Contents of location 5892 are complemented and stored in location 5892

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Q#27 Microprocessor GATE EC 2004 (Set 1) MCQ +2 marks -0.66 marks

It is desired to multiply the numbers 0AH by 0BH and store the result in the accumulator. The numbers are available in registers B and C respectively. A part of the 8085 program for this purpose is given below:

The sequence of instruction to the complete the program would be

JNZ LOOP, ADD B, DCR C

ADD B, JNZ LOOP, DCR C

DCR C, JNZ LOOP, ADD B

ADD B, DCR C, JNZ LOOP

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Q#28 Microprocessor GATE EC 2003 (Set 1) MCQ +2 marks -0.66 marks

In an 8085 microprocessor, the instruction CMP B has been executed while the content of the accumulator is less than that of register B. As a result

Carry flag will be set but zero flag will be reset

Carry flag will be reset but zero flag will be set

Both Carry flag and zero flag will be reset

Both Carry flag and zero flag will be set

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Q#29 Microprocessor GATE EC 2002 (Set 1) MCQ +2 marks -0.66 marks

Consider the following assembly language program.          


The execution of the above program in an 8085 microprocessor will result in

An output of 87H at PORT1

An output of 87H at PORT2

Infinite looping of the program execution with accumulator data remaining at 00H

Infinite looping of the program execution with accumulator data altering between 00H and 87H

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Q#30 Microprocessor GATE EC 2002 (Set 1) MSQ +2 marks -0 marks

An 8085 microprocessor operating at 5 MHz clock frequency execute the following routine.
(a) Determine the total number of machine cycles required to execute this routine till the JMP instruction is executed for the first time.

(b) Determine the time interval between two consecutive  signals.

(c) If the external logic controls the READY line so that three WAIT states are introduced in the I/O WRITE machine cycle, determine the time interval between two consecutive  signals.

(a) 9 machine cycles

(b) Time required =  8.2 µsec

(c) Time required =  8.6 µsec

(c) Time required =  8.8 µsec

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Q#31 Microprocessor GATE EC 2001 (Set 1) MCQ +1 mark -0.33 marks

An 8085 microprocessor based system uses a 4K × 8-bit RAM whose starting address is AA00. The address of the last byte in this RAM is

0FFF H

1000 H

B9FF H

BA00 H

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Q#32 Microprocessor GATE EC 2001 (Set 1) MSQ +2 marks -0 marks

Consider the following sequence of instructions for an 8085 microprocessor-based system:


(a) If the program execution begins at the location FF00 H, write down the sequence of instructions which are actually executed till a HLT instruction. (Assume all flags are initially RESET)

(b) Which of three ports (PORT1, PORT2 and PORT3) will be loaded with the data and what is the bit pattern of the data?

(a) The actual sequence of instructions being executed is,

(b) PORT 2 is loaded with output data and the bit pattern is 0000 0011

(b) PORT 3 is loaded with output data and the bit pattern is 0000 0011

None

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Q#33 Microprocessor GATE EC 2000 (Set 1) MCQ +2 marks -0.66 marks

The contents of Register (B) and Accumulator (A) of 8085 microprocessor are 49H and 3AH respectively. The contents of A and the status of carry flag (CY) and sign flag (S) after executing SUB B instructions are        

A = F1, CY = 1, S = 1

A = 0F, CY = 1, S = 1

A = F0, CY = 0, S = 0

A = 1F, CY = 1, S = 1

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Q#34 Microprocessor GATE EC 2000 (Set 1) MCQ +1 mark -0.33 marks

The number of hardware interrupts (which require an external signal to interrupt) present in an 8085 microprocessor are

1

4

5

13

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Q#35 Microprocessor GATE EC 2000 (Set 1) MCQ +1 mark -0.33 marks

In the 8085 microprocessor, the RST6 instruction transfers the program execution to the following location

30 H

24 H

48 H

60 H

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Q#36 Microprocessor GATE EC 2000 (Set 1) MSQ +2 marks -0 marks

(a) The program and machine code for an 8085 microprocessor are given by        

The starting address of the above program is 7FFF H. What would happen if it is executed from 8000 H?

(b) For the instructions given below, how many memory operations (read/write) are performed during the execution in an ?

(c) Write an instruction which takes the minimum possible time to clear the accumulator of the 8085.

(a) The program jumps to original location 8000H and stays in that location as infinite loop.

(b) Total memory read/write = 13

(b) Total memory read/write = 12

(c) XRA A

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Q#37 Microprocessor GATE EC 1999 (Set 1) MCQ +2 marks -0.66 marks

If  is used as the chip select logic of a 4 KRAM in an 8085 system, then its memory range will be

3000 H – 3 FFF H

7000 H – 7 FFF H

5000 H – 5 FFF H and 6000 H – 6 FFF H

6000 H – 6 FFF H and 7000 H – 7 FFF H

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Q#38 Microprocessor GATE EC 1999 (Set 1) MSQ +2 marks -0 marks

An 8085 assembly language program is given below:         

Contents of the memory locations 2000 H to 2002H are: 

2000 : 18 H        2001 : 10H        2002 : 2BH

(a) What does the above program do?

(b) At the end of the program, what will be

(i) The contents of the registers A, B, C ,H and L?

(ii) The condition of the carry and zero flags?

(iii) The contents of the memory locations 2000 H,         2001 H , 2002 H and 2100 H.

This program will find the highest number among all the three memory locations present in the given memory location, finally that highest number will present in the accumulator which will then be stored at the memory location 2100H.

This program will find the lowest number among all the three memory locations present in the given memory location, finally that lowest number will present in the accumulator which will then be stored at the memory location 2100H.

A = 2BH
B = 2BH
C = 00H
HL = 2002H

CY=1 and Z = 1

2000H : 18H

2001H : 10H

2002H : 2BH

2100H : 2BH

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Q#39 Microprocessor GATE EC 1998 (Set 1) MCQ +2 marks -0.66 marks

 An I/O processor control the flow of information between

Cache memory and I/O devices

Main memory and I/O devices

Two I/O devices

Cache and main memories

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Q#40 Microprocessor GATE EC 1998 (Set 1) MCQ +2 marks -0.66 marks

Write a short assembly language program, without using any arithmetic instruction, to store hexadecimal 5D in the flag register of 8085 microprocessor. Data in other registers of the processor must not alter upon executing this program.

PUSH D
PUSH H

MOV L, A
MVI E, 5D

PUSH D

MOV A, L

POP H

POP D

PUSH D
PUSH H

MOV L, A
MVI E, 5D

PUSH D

POP PSW
MOV A, L

POP H

POP D

PUSH D
PUSH H

MOV L, A

PUSH D

POP PSW
MOV A, L

POP H

POP D

None of these

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Q#41 Microprocessor GATE EC 1998 (Set 1) MCQ +2 marks -0.66 marks

An instruction used to set the carry Flag in a computer can be classified as

Data transfer

Arithmetic

Logical

Program control

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Q#42 Microprocessor GATE EC 1997 (Set 1) MCQ +1 mark -0.33 marks

In an  system, the RST instruction will cause an interrupt

Only if an interrupt service routine is not being executed

Only if a bit in the interrupt mask is made 0

Only if interrupts have been enabled by an EI instruction

None of the above

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Q#43 Microprocessor GATE EC 1997 (Set 1) MCQ +1 mark -0.33 marks

The following instructions have been executed by an 8085 .

From which address will the next instruction be fetched?

6019

6379

6979

None of the above

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Q#44 Microprocessor GATE EC 1997 (Set 1) MCQ +1 mark -0.33 marks

A signed integer has been stored in a byte using the 2’s complement format. We wish to store the same integer in a 16 bit word. We should

Copy the original byte to the less significant byte of the word and fill the more significant with zeros

Copy the original byte to the more significant byte of the word and fill the less significant byte with zeros

Copy the original byte to the less significant byte of the word and make each fit of the more significant byte equal to the most significant bit of the original byte

Copy the original byte to the less significant byte as well as the more significant byte of the word

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Q#45 Microprocessor GATE EC 1997 (Set 1) MSQ +2 marks -0 marks

While moving data between registers of the 8085 and the stack

(1) A PUSH instruction

(2) A POP instruction

Pre increments the stack pointer

Post increments the stack pointer

Pre decrements the stack pointer

Post decrements the stack pointer

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Q#46 Microprocessor GATE EC 1997 (Set 1) NAT +2 marks -0 marks

An  uses a 2 MHz crystal. Find the time taken by it to execute the following delay subroutine, inclusive of the call instruction in the calling program.

You are given that a CALL instruction takes 18 cycles of the system clock, PUSH requires 12 cycles and a conditional jump takes 10 cycles if the jump is taken and 7 cycles if it is not. All other instructions used
above take
 clock cycles, where n is the number of accesses to the memory, inclusive of the op-code fetch.

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Q#47 Microprocessor GATE EC 1996 (Set 1) MCQ +1 mark -0.33 marks

The total number of memory accesses involved (inclusive of the op-code fetch) when an 8085 processor executes the instruction LDA 2003 is

1

2

3

4

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Q#48 Microprocessor GATE EC 1995 (Set 1) MCQ +1 mark -0.33 marks

When CPU is interrupted, it

Stops execution of instructions

Acknowledges interrupt and branches of sub-routine

Acknowledges interrupt and continues

Acknowledges interrupt and wait for the next instruction from the interrupting device

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Q#49 Microprocessor GATE EC 1995 (Set 1) MCQ +1 mark -0.33 marks

A ‘DMA’ transfer implies        

Direct transfer of data between memory and accumulator

Direct transfer of data between memory and I/O devices without the use of

Transfer of data exclusively within  registers

A fast transfer of data between  and I/O devices

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Q#50 Microprocessor GATE EC 1995 (Set 1) MCQ +1 mark -0.33 marks

An ‘Assembler’ for a microprocessor is used for

Assembly of processors in a production line

Creation of new programmes using different mo-dules

Translation of a program from assembly language to machine language

Translation of a higher level language into English text

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Q#51 Microprocessor GATE EC 1993 (Set 1) MCQ +2 marks -0.66 marks

In a microprocessor, the register which holds the address of the next instruction to be fetched is:        

Accumulator

program counter

stack pointer

 instruction register

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Q#52 Microprocessor GATE EC 1993 (Set 1) MCQ +2 marks -0.66 marks

 In a microcomputer, wait states are used at

Make the processor wait during a DMA operation.

Make the processor wait during an interrupt processing

Make the processor wait during a power shutdown

Interface slow peripherals to the processor

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Q#53 Microprocessor GATE EC 1993 (Set 1) MSQ +2 marks -0 marks

A microprocessor has five address lines  and eight data lines . An input device A, an output device B, A ROM and a RAM are memory mapped to the microprocessor at the addresses as shown in figure.
38.jpg

Devices A and B have four addressable registers each; RAM has 8 bytes and ROM has 16 bytes.

Obtain the minimum sum of product expression for the chip select (CS) function of each device/memory.

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Q#54 Microprocessor GATE EC 1992 (Set 1) MCQ +2 marks -0.66 marks

In an 8085 microprocessor system with memory mapped I/O,

I/O devices have 16 bit addresses

I/O devices are accessed using IN and OUT instructions

There can be a maximum of 256 input devices and 256 output devices

Arithmetic and logic operations can be directly performed with the I/O data.

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Q#55 Microprocessor GATE EC 1992 (Set 1) MSQ +1 mark -0 marks

The following program is run on 8085 microprocessor:

At the completion of execution of the program, the program Counter of the 8085 contains __________ and the Stack Pointer contains __________.

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Q#56 Microprocessor GATE EC 1992 (Set 1) MSQ +2 marks -0 marks

Figure shows the memory circuit of an 8085 microprocessor.

(a) What is the total size of the memory in the circuit?

(b) What are the beginning and ending addresses of the memory in chip 1?

(Give the answer in hexadecimal numbers)

(c) What are the beginning and ending addresses of the memory in chip 2?

(d) Are the memory chips in the circuit ROM or RAM?

(e) How will you replace the two NAND gates in the circuit with one 3 to 8 decoder without changing the memory addresses? Assume that the decoder has one active high enable  and one active low enable .

Total size of memory
The chips used in the circuit are ROM

Beginning and ending addresses of the memory in chip 1

Beginning and ending addresses of the memory in chip 2

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Q#57 Microprocessor GATE EC 1991 (Set 1) MSQ +2 marks -0 marks

The program given below is run on an 8085 based microcomputer system. Determine the contents of the registers: PC, SP, B, C, H, L after a halt instruction is executed.

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