Select the correct statement(s) regarding CMOS implementation of NOT gates.

In the circuit shown, A and B are the inputs and F is the output. What is the functionality of the circuit?

In the circuit shown, what are the values of F for EN=0 and EN=1, respectively?

A standard CMOS inverter is designed with equal rise and fall times. If the width of the pMOS transistor in the inverter is increased, what would be the effect on the LOW noise marginand the HIGH noise margin?

The logic function realized by the given circuit is

For the circuit shown in the figure, P and Q are the inputs and Y is the output.

The logic implemented by the circuit is

What is the voltage  in the following circuit?

Transistor geometries in a CMOS inverter have been adjusted to meet the requirement for worst case charge and discharge times for driving a load capacitor C. This design is to be converted to that of a NOR circuit in the same technology, so that its worst case charge and discharge times while driving the same capacitor are similar. The channel lengths of all transistors are to be kept unchanged. Which one of the following statements is correct?

The logic functionality realized by the circuit shown below is

The output (Y) of the circuit shown in the figure is

In the circuit shown, diodes ,  and  are ideal, and the inputs ,  and  are “0 V” for logic ‘0’ and “10 V” for logic ‘1’. What logic gate does the circuit represent?

In the circuit shown below  has negligible collector-to-emitter saturation voltage and the diode drops negligible voltage across it under forward bias. If  as logic 1, then the Boolean expression for Z is        

In the circuit shown        

The full forms of the abbreviations TTL and CMOS in reference to logic families are

The logic function implemented by the following circuit at the terminal OUT is        

The circuit diagram of a standard TTL NOT gate is shown in the figure. When , the modes of operation of the transistors will be

The transistors used in a portion of the TTL gate shown in figure have . The base-emitter voltage of is 0.7V for a transistor in active region and 0.75V for a transistor in saturation. If the sink current I=1mA and the output is at logic 0, then the current  will be equal to

Figure shows the internal schematic of a TTL AND-OR-Invert (AOI) gate. For the inputs shown in Figure, the output Y is

Figure is the voltage transfer characteristic of

The output of the 74 series of TTL gates is taken from a BJT in

The DTL, TTL, ECL and CMOS families of digital ICs are compared in the following 4 columns          

The correct column is

Consider the following statements in connection with the CMOS inverter in figure where both the MOSFETs are of enhancement type and both have a threshold voltage of 2V.

Statement 1:  conducts when

Statement 2:  is always in saturation when

Which of the following is correct?

Each transistor in Figure has dc current gain , cut-in voltage  and . The output voltage  for  in saturation can be as high as 0.2 V. Assume 0.7 V drop across a conducting p-n junction. Determine         

(a) The minimum level  necessary to keep  saturation.

(b) The maximum permissible value for the resistance .

(c) The worst-case high input (logic 1) and the worst-case low input (logic 0) for which   will be either in saturation or in cut off.

In Figure, the LED

A Darlington emitter-follower circuit is sometimes used in the output stage of a TTL gate in order to

Commercially available ECL gates use two ground lines and one negative supply in order to

In the CMOS inverter circuit shown in Figure, the input  makes a transition from  to . Determine the high-to-low propagation delay time (μsec). when it is driving capacitance load  of 20pF. Device data:

NMOS: ; , ,

PMOS: ; , .

Neglect body effect.

The noise margin of a TTL gate is about         

The threshold voltage for each transistor in Figure is 2V. For this circuit to work as an inverter  must take the values

For the TTL circuit shown in Figure, find the current (μA)through the collector of transistor  When .

Assume,  and , the of  in its inverse active mode is 0.01.]                

In standard TTL, the ‘totem pole’ stage refers to

The inverter 74 ALSO4 has the following specifications

,

, ,

,

The fan out based on the above will be        

For the NMOS logic gate shown in the figure is the logic function implemented is

Find static Noise-Margins for a BJT inverter shown in the figure is Transistor used is an n-p-n type with specifications as follows

Also                 

 and

Supply.        

Schottky clamping is resorted in TTL gates

For a TTL gate, match the following

(A)

(B)

(C)

(1) 2.4 volts

(2) 1.5 volts

(3) 0.4 volts

(4) 2.0 volts

(5) 0.8 volts

In the output stage of a standard TTL, have a diode between the emitter of the pull-up transistor and the collector of the pull-down transistor. The purpose of this diode is to isolate the output node from the power supply  ( True=1, False=0)

The figure shows the circuit of a gate in the Resistor Transistor Logic (RTL) family. The circuit represents a

The CMOS equivalent of the following NMOS gate (in figure) is ____________ (draw the circuit).        

In figure, the Boolean expression for the output in terms of inputs A, B and C when the clock ‘CK’ is high, is given by