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Electronic Devices
Fabrication

Practice questions from Fabrication.

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Q#1 Fabrication GATE EC 2019 (Set 1) MCQ +1 mark -0.33 marks

The correct circuit representation of the structure shown in the figure is

14.tif

15.tif

16.tif

17.tif

18.tif

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Q#2 Fabrication GATE EC 2018 (Set 1) NAT +1 mark -0 marks

There are two photolithography systems: one with light source of wavelength (System 1) and another with light source of wavelength (System 2). Both photolithography systems are otherwise identical. If the minimum feature sizes that can be realized using System1 and System2 are  and  respectively, the ratio (correct to two decimal places) is

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Q#3 Fabrication GATE EC 2015 (Set 3) MCQ +1 mark -0.33 marks

Which one of the following processes is preferred to form the gate dielectric  of MOSFETs?

Sputtering

Molecular beam epitaxy

Wet oxidation

Dry oxidation

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Q#4 Fabrication GATE EC 2014 (Set 2) MCQ +1 mark -0.33 marks

In CMOS technology, shallow P-well or N-well regions can be formed using

Low pressure chemical vapour deposition

Low energy sputtering

Low temperature dry oxidation

Low energy ion-implantation

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Q#5 Fabrication GATE EC 2013 (Set 1) MCQ +1 mark -0.33 marks

In IC technology, dry oxidation (using dry oxygen) as compared to wet oxidation (using steam or water vapor) produces

Superior quality oxide with a higher growth rate

Inferior quality oxide with a higher growth rate

Inferior quality oxide with a lower growth rate

Superior quality oxide with a lower growth rate

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Q#6 Fabrication GATE EC 2008 (Set 1) MCQ +1 mark -0.33 marks

A silicon wafer has  of oxide on it and is inserted in a furnace at a temperature above  for further oxidation in dry oxygen. The oxidation rate

Is independent of current oxide thickness and temperature

Is independent of current oxide thickness but depends on temperature

Slow down as the oxide grows

Is zero as the existing oxide prevents further oxidation

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Q#7 Fabrication GATE EC 2003 (Set 1) MCQ +2 marks -0.66 marks

If P is Passivation, Q is n-well implant, R is metallization and S is source/drain diffusion, then the order in which they are carried out in a standard n-well CMOS fabrication process, is

P-Q-R-S

Q-S-R-P

R-P-S-Q

S-R-Q-P

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