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Q#1
Logic Family
GATE EC 2019
MCQ
+1 mark
-0.33 marks
A standard CMOS inverter is designed with equal rise and fall times
. If the width of the pMOS transistor in the inverter is increased, what would be the effect on the LOW noise margin
and the HIGH noise margin
?
decreases andincreases
Bothandincrease
No change in the noise margin
increases anddecreases
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