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Practice over 1000+ GATE-level questions from this topic!

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Q#1 Logic Family GATE EC 1999 NAT +2 marks -0 marks

In the CMOS inverter circuit shown in Figure, the input  makes a transition from  to . Determine the high-to-low propagation delay time (μsec). when it is driving capacitance load  of 20pF. Device data:

NMOS: ; , ,

PMOS: ; , .

Neglect body effect.

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