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Q#1 Combinational Circuits GATE EC 2015 MCQ +2 marks -0.66 marks

A 1-to-8 de-multiplexer with data input  , address inputs  (with  as the LSB) and  and as the eight de-multiplexed outputs, is to be designed using two 2-to-4 decoders (with enable input  and address inputs  and ) as shown in the figure.  and  are to be connected to P, Q, R and S, but not necessarily in this order. The respective input connections to P, Q, R, and S terminals should be        

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