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Q#1
Combinational Circuits
GATE EC 2014
NAT
+2 marks
-0 marks
A 16-bit ripple carry adder is realized using 16 identical full adders (FA) as shown in the figure. The carry-propagation delay of each FA is 12 ns and the sum-propagation delay of each FA is 15ns. The worst case delay (in ns) of this 16-bit adder will be __________.
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