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Q#1
Sequential Circuits
GATE EC 2003
MCQ
+2 marks
-0.66 marks
A 4 bit ripple counter and a 4 bit synchronous counter are made using flip-flops having a propagation delay of 10 ns each. If the worst case delay in the ripple counter and the synchronous counter be R and S respectively, then
R = 10 ns, S = 40 ns
R = 40 ns, S = 10 ns
R = 10 ns, S = 30 ns
R = 30 ns, S = 10 ns
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