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Q#1
Sequential Circuits
GATE EC 2025
MCQ
+2 marks
-0.66 marks
A positive-edge-triggered sequential circuit is shown below. There are no timing violations in the circuit. Input 
is set to logic ' 0 ' and 
is set to logic ' 1 ' at all times. The timing diagram of the inputs 
and 
are also shown below.
The sequence of output 
from time 
to 
is ________.
1011
0100
0010
1101
Explanation:
Label left 
as 
and right 
Y=1011
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