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Practice over 1000+ GATE-level questions from this topic!

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Q#1 Sequential Circuits GATE EC 2016 NAT +1 mark -0 marks

Assume that all the digital gates in the circuit shown in the figure are ideal, the resistor  and the supply voltage is 5V. The D flip-flops ,,,  and  are initialized with logic values 0,1,0,1 and 0, respectively.  The clock has a 30% duty cycle.

The average power dissipated (in mW) in the resistor R is ________.

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