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Q#1
Data Converters
GATE EC 2014
MCQ
+1 mark
-0.33 marks
For a given sample-and-hold circuit, if the value of the hold capacitor is increased, then
Droop rate decreases and acquisition time decreases
Droop rate decreases and acquisition time increases
Droop rate increases and acquisition time decreases
Droop rate increases and acquisition time increases
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