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Q#1
Sequential Circuits
GATE EC 2006
MCQ
+2 marks
-0.66 marks
For the circuit shown in figure below, two 4-bit parallel-in serial-out shift registers loaded with the data shown are used to feed the data to a full adder. Initially, all the flip-flops are in clear state. After applying two clock pulses, the output of the full-adder should be
S = 0 
S = 0 
S = 1
S = 1
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