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Q#1
Sequential Circuits
GATE EC 2016
MCQ
+2 marks
-0.66 marks
For the circuit shown in the figure, the delay of the bubbled NAND gate is 2 ns and that of the counter is assumed to be zero.
If the clock (CLK) frequency is 1 GHz, then the counter behaves as a
mod-5 counter
mod-6 counter
mod-7 counter
mod-8 counter
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