In the circuit shown in Figure, A is a parallel-in, parallel-out 4-bit register, which loads at the rising edge of the clock C. The input lines are connected to a 4-bit bus, W. Its output acts as the input to a 16×4 ROM whose output is floating when the enable input E is 0. A partial table of contents of the ROM is as follows:

The clock to the register is shown, and the data on the W bus at time  is 0110. The data on the bus at time  is