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Q#1 MOSFET - EDC GATE EC 2012 MCQ +2 marks -0.66 marks

In the three dimensional view of a silicon n-channel MOS transistor shown below, δ= 20 nm. The transistor is of width 1μm. The depletion width formed at every p-n junction is 10 nm. The relative permittivities of Si and  , respectively, are 11.7 and 3.9, and ,= 8.9 x  F/m.        

Q50

The gate-source overlap capacitance is approximately        

0.7fF

0.7pF

0,35fF

0.24pF

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