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Q#1
Sequential Circuits
GATE EC 2009
MCQ
+2 marks
-0.66 marks
Refer to the NAND and NOR latches shown in the figure. The inputs 1 for both the latches are first made (0, 1) and then, after a few seconds, made (1, 1). The corresponding stable outputs 
are
NAND: first (0, 1) then (0, 1)
NOR: first (1, 0) then (0, 0)
NAND: first (1, 0) then (1, 0)
NOR: first (1, 0) then (1, 0)
NAND: first (1, 0) then (1, 0)
NOR: first (1, 0) then (0, 0)
NAND: first (1, 0) then (1, 1)
NOR: first (0, 1) then (0, 1)
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