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Practice over 1000+ GATE-level questions from this topic!

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Q#1 Sequential Circuits GATE EC 2021 NAT +2 marks -0 marks

The propagation delay of the exclusive-OR (XOR) gate in the circuit in the figure is . The propagation delay of all the flip-flops is assumed to be zero. The clock (Clk) frequency provided to the circuit is .

Starting from the initial value of the flip-flop outputs  with , the minimum number of triggering clock edges after which the flip-flop outputs  becomes 100 (in integer) is _________.

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