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Q#1
Combinational Circuits
GATE EE 2003
MCQ
+1 mark
-0.33 marks
Figure shows a 4 to 1 MUX to be used to implement the sum S of a 1-bit full adder with input bits P and Q and the carry input. Which of the following combinations of inputs to and of the MUX will realize the sum S?
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Browse Practice Questions by Chapters / Topics in Browse Practice Questions by Chapters / Topics in GATE Electrical Engineering
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| Topic | Questions | Attempted | Correct | |
|---|---|---|---|---|
| Network Analysis | 268 | 0 | 0 | |
| Signals and Systems | 168 | 0 | 0 | |
| Control Systems | 262 | 0 | 0 | |
| Analog Electronics | 186 | 0 | 0 | |
| Digital Electronics | 150 | 0 | 0 | |
| Electrical Machines | 399 | 0 | 0 | |
| Power Electronics | 243 | 0 | 0 | |
| Power Systems | 350 | 0 | 0 | |
| EMFT EE | 111 | 0 | 0 | |
| Measurement | 160 | 0 | 0 | |
| Engineering Mathematics | 236 | 0 | 0 | |
| General Aptitude | 221 | 0 | 0 |
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