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Q#1
Fault Analysis
GATE EE 2025
NAT
+1 mark
-0 marks
The bus impedance matrix of a 3-bus system (in pu) is
A symmetrical fault (through a fault impedance of 
) occurs at bus 2. Neglecting pre-fault loading conditions, the voltage at bus 1 , during the fault is __________ pu (round off to three decimal places).
Explanation:
when the fault occurs at bus-2,
Voltage at bus -1, 
(during fault) 
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