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Q#1 Sinusoidal Steady State Analysis GATE EE 2006 MCQ +2 marks -0.66 marks

The circuit shown in the figure is energized by a sinusoidal voltage source  at a frequency which causes resonance with a current of I.

C:\Users\Ankit\Dropbox\GATE papers\EE papers\Typed\Gate-EE-2006\Figures\Q32-1.jpg

The phasor diagram which is applicable to this circuit is

Q32-2.jpg

Q32-3.jpg

Q32-4.jpg

Q32-5.jpg

Explanation:

Various resistances and impedances have been marked in the circuit shown below,

Untitled-7.png

At resonance,         

I is in phase with

At resonance

 is also in phase with  and less than

Hence the phasor diagram is,

C:\Users\Ankit\Dropbox\GATE papers\EE papers\Solutions\network\Network\Network\network 2006\Untitled-8.png

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