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Q#1
Sequential Circuits
GATE EE 2016
MCQ
+2 marks
-0.66 marks
The current state 
of a two JK flip-flop system is 00. Assume that the clock rise-time is much smaller than the delay of the JK flip-flop. The next state of the system is
00
01
11
10
Explanation:
The JK inputs of the first flip flop are both pulled high and the JK inputs of the second flip flop are connected to 
which is initially 1.
When 
, it is toggle condition.
So output of both the flip-flops will be change to 1 in the next state.
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