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Q#1
Logic Family
GATE EE 2017
MCQ
+2 marks
-0.66 marks
The logical gate implemented using the circuit shown below where, V1 and V2 are inputs (with 0 V as digital 0 and 5 V as digital 1) and VOUT is the output, is
NOT
NOR
NAND
XOR
Explanation:
If either 
or 
is logic 1; the transistor turns ON &
If both
, the output is large 1
Hence, the logic implements a NOR gate
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