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Q#1
Combinational Circuits
GATE EE 1997
MCQ
+2 marks
-0.66 marks
A 3-input 2-output priority encoder has the following truth table where X’s indicate don’t care conditions. Realize the logic using NAND gates and inverters
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0 | 0 | 0 | 0 | 0 |
0 | 0 | 1 | 0 | 0 |
0 | 1 | X | 1 | 0 |
1 | X | X | 1 | 1 |
Explanation:
K-Map for 
K-Map for 
Realization of logic
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