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Q#1 Transient Analysis GATE EE 2009 MCQ +2 marks -0.66 marks

In the figure shown, all elements used are ideal. For time t < 0, \(S_1\) remained closed and \(S_2\) open. At
t = 0, 
\(S_1\) is opened and \(S_2\) is closed.  If the voltage \(Vc_2\) across the capacitor \(C_2\) at t = 0 is zero, the voltage across the capacitor combination at  will be

Q22.jpg

1V

2V

1.5V

3V

Explanation:

For t < 0, the circuit configuration is shown below,

Untitled-9.png

Since voltage across capacitor doesn’t change immediately

At , the circuit configuration is shown below,

Untitled-10.png

Change stored in  before t=0

Since, there is no resistor in the circuit, the charge shall remain conserved.

So, charge stored after t=0 in the combination of capacitor

Since voltage across both capacitor will be identical as both are in parallel

From equation (1) & (2)

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